1. Technical Field
The present invention relates to memory hard failure repair, and more specifically, to hard failure repair during normal operation using an ECC (Error Correction Code) circuit and a hard fail identifier circuit.
2. Related Art
Prior art exists which covers detection and repair of hard failures in a memory device during the manufacturing process (i.e., at time zero). Prior art also exists which covers detection and correction of soft errors in a memory device during normal operation (e.g., Error Correction Code). Prior art also exists which covers memory error detection and address disable or device replacement during normal operation. There is a need for a subsystem (and a method for operating the same) in which hard failures are detected and repaired during normal operation of a memory device.